FIG. 4 is an explanation drawing showing an MOS transistor conceptually. As shown in this drawing, the MOS transistor has two p-regions formed on an n-type silicon substrate 04, a source electrode 01 and a drain electrode 02 formed in the respective p-regions, and a gate electrode 03 formed on the n-type silicon substrate 04 via a gate insulating film 05 which is a SiO2 film. Such an MOS transistor having a NiSi film formed as the source electrode 01, the drain electrode 02 or the gate electrode 03 is produced.
In this case, heat treatment at 450° C. is necessary for silicidization of Ni. However, Ni which has been deposited for the formation of NiSi, or an impurity with which a semiconductor has been doped, may be diffused to cause defects in device manufacturing, or deterioration of characteristics.
To solve such problems, the following complicated process has been proposed: First, heat treatment at 400° C. is performed to form a mixture of a nickel-rich silicide, such as Ni2Si, and Si at the desired site (gate electrode portion). Surplus Ni is removed by wet etching, and then heat treatment at 450° C. is performed to form complete NiSi.
Such a process involves the problems that the number of steps is large, and the treating temperature is still high. The higher the treating temperature, the more likely it is that problems will occur, such as the degradation of performance of the MOS transistor due to the diffusion of the doped impurity or the deterioration of insulation in the gate insulating film 05.
The following are present as documents disclosing the above-described conventional technologies:
Patent Document 1: Japanese Unexamined Patent Publication No. 2005-019705
Patent Document 2: Japanese Unexamined Patent Publication No. 2004-165627
Patent Document 3: Japanese Unexamined Patent Publication No. 1997-059013